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- W2552838705 abstract "Irreducible polynomial algorithm for modular multiplication with a large modulus has been widely used for error control coding in secured data communication. This paper presents an area-time efficient bit-parallel systolic multiplication architecture over GF (2 m ) based on irreducible all-one polynomial. This circuit is constructed by identical cells, each of which consists of one two-input AND gate, one two-input XOR gate and Bit shift cell. The proposed architecture is well suited to VLSI systems due to their regular interconnection pattern and modular structure." @default.
- W2552838705 created "2016-11-30" @default.
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- W2552838705 date "2013-01-01" @default.
- W2552838705 modified "2023-09-26" @default.
- W2552838705 title "SYSTOLIC ALL ONE POLYNOMIAL MULTIPLIER FOR REED-SOLOMON ENCODER" @default.
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- W2552838705 hasPublicationYear "2013" @default.
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