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- W2553034289 abstract "Within this work, we apply Razor to hardware accelerators that find growing application in System-on-Nick designs rich in-performance needs that must definitely be delivered under stringent power budgets. We exploit these traits usual for DSP and image-processing accelerators to apply Razor recovery in manner that's amenable to RTL validation and verification. We describe the implementation and plastic measurement is a result of a Razor-based hardware loop-accelerator (RZLA), applying the Sobel edge-recognition formula. Unlike microprocessors, the RZLA pipeline is data path-dominated with statically-scheduled control which has queue-based storage structures that are simply extended to aid check-pointing and recovery. The RFF is deployed along with an amount-sensitive latch-insertion based formula to deal with the minimum-delay constraint contained in all Razor systems. This formula enables using the time period for timing speculation resulting in robust error recognition and correction across a large dynamic current- and frequency-scaling range." @default.
- W2553034289 created "2016-11-30" @default.
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- W2553034289 date "2016-11-18" @default.
- W2553034289 modified "2023-09-28" @default.
- W2553034289 title "AN INFORMATIVE PIPELINING WITH SCHEDULING REGULATOR TO SUPPORT RECOVERY" @default.
- W2553034289 hasPublicationYear "2016" @default.
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