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• W2554031552 abstract "In advanced technology nodes, physical design engineers must estimate whether a standard-cell placement is routable (before invoking the router) in order to maintain acceptable design turnaround time. Modern SoC designs consume multiple compute servers, memory, tool licenses and other resources for several days to complete routing. When the design is unroutable, resources are wasted, which increases the design cost. In this work, we develop machine learning-based models that predict whether a placement solution is routable without conducting trial or early global routing. We also use our models to accurately predict iso-performance Pareto frontiers of utilization, aspect ratio and number of layers in the back-end-of-line (BEOL) stack. Furthermore, using data mining and machine learning techniques, we develop new methodologies to generate training examples given very few placements. We conduct validation experiments in three foundry technologies (28nm FDSOI, 28nm LP and 45nm GS), and demonstrate accuracy ≥ 85.9% in predicting routability of a placement. Our predictions of Pareto frontiers in the three technologies are pessimistic by at most 2% with respect to the maximum achievable utilization for a given design in a given BEOL stack." @default.
• W2554031552 created "2016-11-30" @default.
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• W2554031552 date "2016-10-01" @default.
• W2554031552 modified "2023-09-27" @default.
• W2554031552 title "BEOL stack-aware routability prediction from placement using data mining techniques" @default.
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• W2554031552 doi "https://doi.org/10.1109/iccd.2016.7753259" @default.
• W2554031552 hasPublicationYear "2016" @default.
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