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• W2554965711 abstract "The increasing demand for smaller, more efficient circuits has created a need for both digital and analog designs to scale down. Digital technologies have been successful in meeting this challenge, but analog circuits have lagged behind due to smaller transistor sizes having a disproportionate negative affect. Since many applications require small, low-power analog circuits, the trend has been to take advantage of digital’s ability to scale by replacing as much of the analog circuitry as possible with digital counterparts. The results are known as digitally-intensive analog/mixed-signal (AMS) circuits. Though such circuits have helped the scaling problem, they have further complicated verification. This dissertation improves on techniques for AMS property specifications, as well as, develops sound, efficient extensions to formal AMS verification methods. With the language for analog/mixed-signal properties (LAMP), one has a simple intuitive language for specifying AMS properties. LAMP provides a more procedural method for describing properties that is more straightforward than temporal logic-like languages. However, LAMP is still a nascent language and is limited in the types of properties it is capable of describing. This dissertation extends LAMP by adding statements to ignore transient periods and be able to reset the property check when the environment conditions change. After specifying a property, one needs to verify that the circuit satisfies the property. An efficient method for formally verifying AMS circuits is to use the restricted polyhedral class of zones. Zones have simple operations for exploring the reachable state space, but they are only applicable to circuit models that utilize constant rates. To extend zones to more general models, this dissertation provides the theory and implementation needed to soundly handle models with ranges of rates. As a second improvement to the state representation, this dissertation describes how octagons can be adapted to model checking AMS circuit models. Though zones have efficient algorithms, it comes at a cost of over-approximating the reachable state space. Octagons have similarly efficient algorithms while adding additional flexibility to reduce the necessary over-approximations. Finally, the full methodology described in this dissertation is demonstrated on two examples. The first example is a switched capacitor integrator that has been studied in the context of transforming the original formal model to use only single rate assignments. Th property of not saturating is written in LAMP, the circuit is learned, and the property is checked against a faulty and correct circuit. In addition, it is shown that the zone extension, and its implementation with octagons, recovers all previous conclusions with the switched capacitor integrator without the need to translate the model. In particular, the method applies generally to all the models produced and does not require the soundness check needed by the translational approach to accept positive verification results. As a second example, the full tool flow is demonstrated on a digital C-element that is driven by a pair of RC networks, creating an AMS circuit. The RC networks are chosen so that the inputs to the C-element are ordered. LAMP is used to codify this behavior and it is verified that the input signals change in the correct order for the provided SPICE simulation traces." @default.
• W2554965711 created "2016-11-30" @default.
• W2554965711 creator A5067086411 @default.
• W2554965711 date "2015-01-01" @default.
• W2554965711 modified "2023-09-23" @default.
• W2554965711 title "Efficient, sound formal verification for analog/mixed-signal circuits" @default.
• W2554965711 cites W1482233117 @default.
• W2554965711 cites W1494737186 @default.
• W2554965711 cites W1498432697 @default.
• W2554965711 cites W1500337659 @default.
• W2554965711 cites W1504065953 @default.
• W2554965711 cites W1505590927 @default.
• W2554965711 cites W1509254601 @default.
• W2554965711 cites W1510918931 @default.
• W2554965711 cites W1522828591 @default.
• W2554965711 cites W1528328008 @default.
• W2554965711 cites W1530746673 @default.
• W2554965711 cites W1532212856 @default.
• W2554965711 cites W1534850143 @default.
• W2554965711 cites W1539343435 @default.
• W2554965711 cites W1542641677 @default.
• W2554965711 cites W1547304883 @default.
• W2554965711 cites W1568322431 @default.
• W2554965711 cites W1568518466 @default.
• W2554965711 cites W1569146343 @default.
• W2554965711 cites W1577323490 @default.
• W2554965711 cites W1580868377 @default.
• W2554965711 cites W1581387743 @default.
• W2554965711 cites W1582385421 @default.
• W2554965711 cites W1585526574 @default.
• W2554965711 cites W1599033249 @default.
• W2554965711 cites W1604596197 @default.
• W2554965711 cites W1662203549 @default.
• W2554965711 cites W1667231716 @default.
• W2554965711 cites W1780005695 @default.
• W2554965711 cites W1964164497 @default.
• W2554965711 cites W1967004917 @default.
• W2554965711 cites W1968813561 @default.
• W2554965711 cites W1994143452 @default.
• W2554965711 cites W1994364444 @default.
• W2554965711 cites W1995691455 @default.
• W2554965711 cites W2002130414 @default.
• W2554965711 cites W2004373311 @default.
• W2554965711 cites W2004463571 @default.
• W2554965711 cites W2023808162 @default.
• W2554965711 cites W2026629052 @default.
• W2554965711 cites W2031188261 @default.
• W2554965711 cites W2032087966 @default.
• W2554965711 cites W2033455284 @default.
• W2554965711 cites W2042801853 @default.
• W2554965711 cites W2047080991 @default.
• W2554965711 cites W2049696538 @default.
• W2554965711 cites W2055606474 @default.
• W2554965711 cites W2061438988 @default.
• W2554965711 cites W2080267935 @default.
• W2554965711 cites W2080884201 @default.
• W2554965711 cites W2084777069 @default.
• W2554965711 cites W2096455207 @default.
• W2554965711 cites W2097451232 @default.
• W2554965711 cites W2097774457 @default.
• W2554965711 cites W2099120582 @default.
• W2554965711 cites W2101508170 @default.
• W2554965711 cites W2101804404 @default.
• W2554965711 cites W2103836778 @default.
• W2554965711 cites W2104439088 @default.
• W2554965711 cites W2104643771 @default.
• W2554965711 cites W2105167627 @default.
• W2554965711 cites W2107164313 @default.
• W2554965711 cites W2116358561 @default.
• W2554965711 cites W2116939169 @default.
• W2554965711 cites W2117350447 @default.
• W2554965711 cites W2120352490 @default.
• W2554965711 cites W2120953717 @default.
• W2554965711 cites W2124292368 @default.
• W2554965711 cites W2124959164 @default.
• W2554965711 cites W2138384911 @default.
• W2554965711 cites W2138839649 @default.
• W2554965711 cites W2142481893 @default.
• W2554965711 cites W2144275718 @default.
• W2554965711 cites W2144785157 @default.
• W2554965711 cites W2148325438 @default.
• W2554965711 cites W2148960955 @default.
• W2554965711 cites W2150377894 @default.
• W2554965711 cites W2151285759 @default.
• W2554965711 cites W2152383599 @default.
• W2554965711 cites W2154128151 @default.
• W2554965711 cites W2156581962 @default.
• W2554965711 cites W2158381251 @default.
• W2554965711 cites W2158533859 @default.
• W2554965711 cites W2159468741 @default.
• W2554965711 cites W2159907637 @default.
• W2554965711 cites W2163590987 @default.
• W2554965711 cites W2165476296 @default.
• W2554965711 cites W2169895193 @default.
• W2554965711 cites W2176215692 @default.
• W2554965711 cites W228833737 @default.
• W2554965711 cites W2298557969 @default.
• W2554965711 cites W2338031113 @default.
• W2554965711 cites W2476720312 @default.
• W2554965711 cites W2485474588 @default.

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