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- W2555222919 abstract "Pre-designed cells, such as buffers, adders and flip-flops are provided by foundries and used in digital circuit design. Actual cell implementation at transistor level is not considered during the synthesis of a digital circuit. The paper describes four cases of transistor-level cell optimisation that can be employed to reach arbitrary customisation. Due to the landscape of the cost functions a global optimisation method was used. The results show that up to 80% improvement of the properties of pre-designed cells can be obtained. Optimizacija gradnikov digitalnih vezij Kjucne besede: nacrtovanje digitalnih integriranih vezij, splosni osnovni gradniki, sinteza digitalnih vezij, optimizacija na tranzistorskem nivoju Izvlecek: Nacrtovalec sestavi digitalno integrirano vezje iz osnovnih gradnikov, kot so medpomnilniki, sestevalniki, flip-flopi ipd. Knjižnico z naborom osnovnih gradnikov zagotovi izdelovalec integriranih vezij. Izvedba posameznega gradnika na tranzistorskem nivoju med postopkom nacrtovanja ni vec pomembna. Clanek se ukvarja z možnostjo prilagoditve posameznega gradnika tocno na zahteve, v katerih deluje. Opisani so stije primeri optimizacije osnovnih gradnikov na tranzistorskem nivoju. Pri tem je bila zaradi narave kriterijske funkcije uporabljena globalna optimizacijska metoda. Tako je možno doseci najboljso prilagoditev gradnika na specificne zahteve. Rezultati kažejo do 80% izboljsanje glede na lastnosti splosnega gradnika, ki ga zagotovi izdelovalec integriranih vezij." @default.
- W2555222919 created "2016-11-30" @default.
- W2555222919 creator A5053517383 @default.
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- W2555222919 date "2010-01-01" @default.
- W2555222919 modified "2023-10-17" @default.
- W2555222919 title "OPTIMISING DIGITAL CIRCUIT CELLS" @default.
- W2555222919 cites W1486006109 @default.
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