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- W2557016603 abstract "In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles." @default.
- W2557016603 created "2016-11-30" @default.
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- W2557016603 date "2008-11-01" @default.
- W2557016603 modified "2023-09-27" @default.
- W2557016603 title "High performance IPC hardware accelerator and communication network for MPSoCs" @default.
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- W2557016603 doi "https://doi.org/10.1109/socdc.2008.4815730" @default.
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