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- W2557367833 abstract "Over the last decade, CUDA and the underlying GPU hardware architecture have continuously gained popularity in various high-performance computing application domains such as climate modeling, computational chemistry, or machine learning. Despite this popularity, we lack a single coherent programming model for GPU clusters. We therefore introduce the dCUDA programming model, which implements device-side remote memory access with target notification. To hide instruction pipeline latencies, CUDA programs over-decompose the problem and over-subscribe the device by running many more threads than there are hardware execution units. Whenever a thread stalls, the hardware scheduler immediately proceeds with the execution of another thread ready for execution. This latency hiding technique is key to make best use of the available hardware resources. With dCUDA, we apply latency hiding at cluster scale to automatically overlap computation and communication. Our benchmarks demonstrate perfect overlap for memory bandwidth-bound tasks and good overlap for compute-bound tasks." @default.
- W2557367833 created "2016-12-08" @default.
- W2557367833 creator A5003890943 @default.
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- W2557367833 date "2016-11-13" @default.
- W2557367833 modified "2023-09-27" @default.
- W2557367833 title "dCUDA: hardware supported overlap of computation and communication" @default.
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- W2557367833 doi "https://doi.org/10.5555/3014904.3014974" @default.
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