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- W2558428614 abstract "The fractional sample interpolation process is one of the most computationally intensive parts of video decoder based on High Efficiency Video Coding (HEVC) standard. Therefore, in this paper, we propose high performance hardware interpolation architecture for inter-prediction which is useful for motion compensation (MC) module in the HEVC decoder. For this component, we propose a highly parallel architecture and a pipelined hardware implementation achieving 8×8 Prediction Unit (PU) interpolation in only 30 clock cycles. Experimental results show that our architecture can achieve up to 3.2 pixels/cycle at 125 MHz on field-programmable gate array technology (FPGA) and the corresponding performance can support the processing of Quad Full High Definition (QFHD, 3840×2160)@30 fps. The gate count of the resulting Application-Specific Integrated Circuit (ASIC) implementation in 65 nm technology is 36.7 k." @default.
- W2558428614 created "2016-12-08" @default.
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- W2558428614 date "2016-09-30" @default.
- W2558428614 modified "2023-09-27" @default.
- W2558428614 title "High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder" @default.
- W2558428614 doi "https://doi.org/10.15866/irecos.v11i9.9753" @default.
- W2558428614 hasPublicationYear "2016" @default.
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