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• W2559500013 abstract "This paper proposes a FPGA based hardware architecture for quadruple precision (QP) division arithmetic which can also process a single, a double and a double-extended precision (SP, DP, DPE) computations. The mantissa division employs a series expansion methodology of division, integrated with a wide integer multiplier further optimized for FPGA implementations facilitating the built-in DSP blocks efficiently. The proposed division architecture is demonstrated using a Xilinx FPGA based implementation has shown a significant area saving and much improvement in latency with improved speed." @default.
• W2559500013 created "2016-12-08" @default.
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• W2559500013 date "2016-07-01" @default.
• W2559500013 modified "2023-10-01" @default.
• W2559500013 title "Architecture for quadruple precision floating point division with multi-precision support" @default.
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• W2559500013 doi "https://doi.org/10.1109/asap.2016.7760807" @default.
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