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- W2560441252 abstract "The Doherty amplifier is a well-known technique for improving efficiency of a power amplifier in a backed off condition. The standard 2 way Doherty amplifier with a peak in efficiency at 6dB back off and full power is commonly used and well understood. With the use of increasingly complex signals comes the requirement to move the peak in efficiency to higher levels of back off whilst maintaining efficiency up to full power output. This can be achieved with asymmetrical Doherty amplifiers or by utilising N-Way Doherty techniques. In this paper we will explain from first principles the operation of the 3 Level Doherty architecture based on an NXP design that uses three LDMOS transistors of equal size. Design challenges faced with this type of amplifier are presented and compared against conventional 3-Way Doherty architecture. Test results are presented which demonstrate a drain efficiency of greater than 40% at 10dB back off." @default.
- W2560441252 created "2016-12-16" @default.
- W2560441252 creator A5040247308 @default.
- W2560441252 date "2016-10-01" @default.
- W2560441252 modified "2023-09-25" @default.
- W2560441252 title "Understanding the 3 level Doherty" @default.
- W2560441252 cites W2099547506 @default.
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- W2560441252 doi "https://doi.org/10.1109/eumic.2016.7777583" @default.
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