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• W2562086301 abstract "Negative Bias Temperature Instability (NBTI) induced transistor aging has become one of the major reliability concerns in sub-micron circuit as technology scales. Transistor performance degrades over time and may eventually cause timing violations and circuit failure. Multi-V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>th</sub> is known as a method to improve circuit performance with leakage and timing tradeoffs. In this paper, we propose a heuristic metric, which could be used to capture leakage and timing tradeoff during multi-V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>th</sub> optimization. Our technique is an after-aging delay minimization problem under leakage power constraint. The experimental results on ISCAS85 benchmark circuits at 45nm node show up to 17% after-aging delay improvement within the predefined leakage power constraint." @default.
• W2562086301 created "2017-01-06" @default.
• W2562086301 creator A5014961146 @default.
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• W2562086301 date "2016-11-01" @default.
• W2562086301 modified "2023-10-16" @default.
• W2562086301 title "Aging-Leakage Tradeoffs Using Multi-Vth Cell Library" @default.
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• W2562086301 doi "https://doi.org/10.1109/ats.2016.13" @default.
• W2562086301 hasPublicationYear "2016" @default.
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