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- W2563920886 abstract "Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias. This paper describes some of the major challenges related to testing of 2.5D ICs and presents some solutions to these problems. We first describe a test architecture using e-fuses for pre-bond interposer testing. We next present an efficient built-in self-test (BIST) technique that targets the dies and the interposer interconnects. Finally, we present a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs." @default.
- W2563920886 created "2017-01-06" @default.
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- W2563920886 date "2016-11-01" @default.
- W2563920886 modified "2023-09-27" @default.
- W2563920886 title "Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions" @default.
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- W2563920886 doi "https://doi.org/10.1109/ats.2016.50" @default.
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