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- W2566242987 abstract "This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 μm CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 μW with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB." @default.
- W2566242987 created "2017-01-06" @default.
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- W2566242987 date "2016-11-01" @default.
- W2566242987 modified "2023-09-23" @default.
- W2566242987 title "Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS" @default.
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- W2566242987 doi "https://doi.org/10.1109/norchip.2016.7792910" @default.
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