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• W2566885839 abstract "We report on the development of energy-efficient decoders for cryogenic random access memory and register file. To reduce the pitch, area, and energy, our decoder employs a scalable binary tree architecture. We implemented these decoders using ERSFQ logic controlled by magnetically coupled address lines. These lines are driven by energy-efficient drivers based on the current-stirring technique. A 4-to-16 version of the decoder was laid out and fabricated in HYPRES 6-layer 10 kA/cm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and MIT LL 8-layer 10 kA/cm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> processes with 15 and 28 μm decoder row pitch, respectively. The decoders were designed to have ~30 ps latency and dissipate ~40 aJ per clock. We experimentally confirmed the functionality of the circuits with ±8% dc bias margins and verified its operation up to 13 GHz clock." @default.
• W2566885839 created "2017-01-06" @default.
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• W2566885839 date "2017-06-01" @default.
• W2566885839 modified "2023-10-06" @default.
• W2566885839 title "Energy-Efficient and Compact ERSFQ Decoder for Cryogenic RAM" @default.
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• W2566885839 doi "https://doi.org/10.1109/tasc.2016.2646926" @default.
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