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- W2567367248 abstract "The method of hardware reduction is proposed which is dedicated for compositional microprogram control unit implemented in CPLD. The method is based on using more than one data source in calculation of microinstruction address. Such approach permits to the decrease the number of logic blocks used for the implementation of the controller in the target CPLD. The paper presents the conditions need ed to apply the method. The article contains a calculation example for the presented method." @default.
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- W2567367248 date "2012-01-01" @default.
- W2567367248 modified "2023-09-26" @default.
- W2567367248 title "OPTIMIZATION OF CMCU WITH BASE STRUCTURE DEDICATED FOR CPLD SYSTEMS" @default.
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