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- W2567573306 abstract "This paper describes the design of a BJT phase-locked loop (PLL) for /spl Sigma//spl Delta/ fractional-N frequency synthesis applications. Implemented in a 0.8 /spl mu/m BiCMOS technology, the PLL can operate up to 1.6 GHz, while consuming 225 mW of power from a single -2 V supply. The LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A low-voltage current-mode logic circuit configuration is used to minimize phase jitter and achieve low-voltage operation. Die size is 4300/spl times/4000 /spl mu/m/sup 2/." @default.
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- W2567573306 date "2002-11-27" @default.
- W2567573306 modified "2023-09-25" @default.
- W2567573306 title "A 2 V 1.6 GHz BJT phase-locked loop" @default.
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- W2567573306 doi "https://doi.org/10.1109/cicc.1998.695041" @default.
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