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- W2567682384 abstract "A detailed numerical and experimental study of the thermal-mechanical stress and strain in the solder bumps (C4s) of a flip-chip ceramic chip carrier has been completed. The numerical model used was based upon the finite element method. The model simulated accelerated thermal cycling (ATC) from 0/spl deg/C to 100/spl deg/C. Several parametric studies were conducted, including the effects of chip size, micro-encapsulation, and the effect of the presence of voids in the micro-encapsulant. It was notably found that the presence of voids in the encapsulant does not significantly increase the stress/strain in the C4s, with the exception of very large voids and voids at or near the edge of the chip." @default.
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- W2567682384 date "1999-01-01" @default.
- W2567682384 modified "2023-10-18" @default.
- W2567682384 title "Void-effect modeling of flip-chip encapsulation on ceramic substrate" @default.
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- W2567682384 doi "https://doi.org/10.1109/6144.814962" @default.
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