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• W2567791849 abstract "This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step." @default.
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• W2567791849 date "2017-01-01" @default.
• W2567791849 modified "2023-10-01" @default.
• W2567791849 title "A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer" @default.
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• W2567791849 doi "https://doi.org/10.4236/cs.2017.81001" @default.
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