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- W2570392076 abstract "This paper presents the measurement and characterization of multi-layered interconnect capacitances for a 0.35 /spl mu/m CMOS logic technology, which is becoming a critical circuit limitation to high performance VLSI design. To measure multi-layered capacitances of interconnect lines, test structures and the measurement methodology are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies." @default.
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- W2570392076 date "2002-11-22" @default.
- W2570392076 modified "2023-09-23" @default.
- W2570392076 title "Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology" @default.
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- W2570392076 doi "https://doi.org/10.1109/icmts.1997.589346" @default.
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