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- W2574248619 abstract "This paper describes a delta-sigma ( ) digital-to- analog converter (DAC) architecture that combines a polyphase de- composition of the interpolation filter and a time-interleaved error- feedback modulator. Noise-shaped oversampling is achieved while clocking the digital circuitry at the Nyquist rate. The de- sign of a third-order 4-bit modulator with eight times oversam- pling using the architecture is presented. Results from a prototype current-DAC driven by a VHDL simulation of the digital design at 2.66 GHz show that 56-dB linearity is achievable in 90-nm CMOS within a 1-V supply over a 155-MHz signal bandwidth making the architecture suitable for emerging ultra-wide-band and 60-GHz radio applications." @default.
- W2574248619 created "2017-01-26" @default.
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- W2574248619 date "2008-01-01" @default.
- W2574248619 modified "2023-09-27" @default.
- W2574248619 title "A Time-Interleaved -DAC Architecture Clocked at the Nyquist Rate" @default.
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