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- W2575790542 abstract "The growing demand of integrating large number of cores on a single chip for faster computation needs faster communication system. Thus Network on chips (NoCs) has provided reliable and scalable solution for communication across cores which mostly use mesh topologies. But 2D NoCs faces the issue of increase in the network diameter which introduces area and power constraints. Thus 3D NoCs has been introduced which provides an alternate interconnect technology and uses the benefits of both NoCs and 3D ICs. 3D NoCs although sustains the performance and growth of increased cores integration but suffer from the issue of faults due to heterogeneous cores integration on different layers, fabrication defects, power saving schemes, component failures etc. which may lead to irregular architecture. Thus to provide efficient routing for such irregular architecture of 3D NoCs is a challenge. This paper extends the capabilities of Segment Routing algorithm by providing formal model for irregular 3D NoCs to enhance its fault tolerance. The Segment Routing is topological agnostic and workable for 2D and 3D meshes but is inefficient for irregular 3D NoCs. The paper extends the concept of segmentation to introduce new segments in Segment Routing algorithm and handles 3D faults using bidirectional turn restrictions. The validation of a Topology Agnostic Routing Algorithm using Segmentation Strategy (TARAS) is performed using theorems which provides concrete definitions to satisfy essential properties of 3D NoCs and enables efficient fault tolerant routing in irregular 3D NoCs." @default.
- W2575790542 created "2017-01-26" @default.
- W2575790542 creator A5032100467 @default.
- W2575790542 date "2016-04-01" @default.
- W2575790542 modified "2023-09-26" @default.
- W2575790542 title "TARAS: A topology agnostic routing algorithm using segmentation strategy for 3D NoC" @default.
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- W2575790542 doi "https://doi.org/10.1109/ccaa.2016.7813981" @default.
- W2575790542 hasPublicationYear "2016" @default.
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