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- W2576538144 abstract "This emergence of the heterogeneous computing is based mainly on various forms of parallel accelerators. We present a family of accelerators for embedded computation with a map-reduce architecture based on the partial recursive functions computation model introduced by Stephen Kleene. A three-level virtual prototyping environment is provided to support the development of embedded applications. The first level is written in a Lisp-like functional language. The second is a C-like environment which segregates the intense part of the computation from the complex part. The last one is a low level simulator able to provide support for advanced optimizations. The environment is designed for developing applications by tuning the architecture of a family of many-core machines which provide high performance per Watt and cm2. The energy efficiency of processors backing our architectural approach is in the range of 10 pJ/flop evaluated for the standard cell 28nm technology." @default.
- W2576538144 created "2017-01-26" @default.
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- W2576538144 date "2016-08-01" @default.
- W2576538144 modified "2023-10-18" @default.
- W2576538144 title "Functional Virtual Prototyping Environment for a Family of Map-Reduce Embedded Accelerators" @default.
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- W2576538144 doi "https://doi.org/10.1109/mcsi.2016.037" @default.
- W2576538144 hasPublicationYear "2016" @default.
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