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- W2577114910 abstract "Near-threshold voltage (V th ) operating circuit is necessary for battery-operated devices. Especially, static random access memory (SRAM) design is important in near-V th region because it is vulnerable to V th variation. The conventional 6T SRAM bitcell design for super-V th operation cannot be used for near-V th operation because V th variation in near-Vth region is more serious than that in super-V th region. In addition, error correction code (ECC) is required to achieve high read stability and write ability yields. In this paper, bitcell yield according to ECC type in SRAM is analyzed and the efficient near-V th bitcell design is determined with considering area overhead in 65nm technology." @default.
- W2577114910 created "2017-01-26" @default.
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- W2577114910 date "2016-10-01" @default.
- W2577114910 modified "2023-09-26" @default.
- W2577114910 title "Low power SRAM bitcell design for near-threshold operation" @default.
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- W2577114910 doi "https://doi.org/10.1109/icce-asia.2016.7804767" @default.
- W2577114910 hasPublicationYear "2016" @default.
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