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- W2579242011 abstract "High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver." @default.
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- W2579242011 date "1990-11-06" @default.
- W2579242011 modified "2023-09-27" @default.
- W2579242011 title "Application specific serial arithmetic arrays" @default.
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