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- W2579777598 abstract "An 8T SRAM bitcell is presented to improve the read stability and writability of SRAM in scaled technologies and low voltages. The presented bitcell achieves a faster access time by increasing the read current by 21% compared to a 6T bitcell. The proposed 8T bitcell utilizes a differential operation, single port and one wordline, therefore, it does not require any architectural changes from 6T SRAM architectures. Moreover, the effects of process-induced V TH variations in multi-threshold 8T bitcells are examined and it is shown that the choice for the best dual-threshold configuration of the proposed 8T bitcell varies due to trade-offs between access time, leakage-power and read/write stability under process variations. In addition, timing variations of the sense amplifier enable signal due to random process variations is reduced by using a Multi Replica Bitline Delay technique to decrease SRAM read access time. The proposed 8T bitcell is demonstrated in a 64 kb SRAM array in 32 nm SOI CMOS technology that operates at 2 GHz at 0.9 V and 250 MHz at 0.3 V." @default.
- W2579777598 created "2017-01-26" @default.
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- W2579777598 date "2016-10-01" @default.
- W2579777598 modified "2023-09-25" @default.
- W2579777598 title "A 64 kb multi-threshold SRAM array with novel differential 8T bitcell in 32 nm SOI CMOS technology" @default.
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- W2579777598 doi "https://doi.org/10.1109/s3s.2016.7804388" @default.
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