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• W2580343488 abstract "Adiabatic logic circuits in weak inversion region or sub threshold region is calculated in deepness for the first time in the reporting to make great improvement in ultra low power circuit design. Adiabatic Logic circuits are operated with an oscillating power supply. The sub-threshold adiabatic logic for VLSI circuits based on power delay product. The voltage scaling method was used to reduce the power consumption. The sub threshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. The 8T static random access memory was designed and also improved both read and write stability in sub threshold region for ultra low power applications. The propose scheme uses a 3T gain cell (GC) dynamic random access memory (DRAM) bit cell that operates with a single-supply voltage and provides more write capability to the predictable GC structures. The propose GC is operated from a single supply voltage, eliminating the boosted voltages. The propose circuit is targeted at low power energy efficient applications. In the propose scheme area will be reduced as compared with the 8T static random access memory. By using TINA and MICROWIND simulator the power consumption and area will be reduced." @default.
• W2580343488 created "2017-02-03" @default.
• W2580343488 creator A5024568332 @default.
• W2580343488 creator A5030523268 @default.
• W2580343488 date "2016-05-01" @default.
• W2580343488 modified "2023-09-25" @default.
• W2580343488 title "Implementation of 3t dram using adiabatic logic for ultra low power applications" @default.
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• W2580343488 doi "https://doi.org/10.1109/icaccct.2016.7831591" @default.
• W2580343488 hasPublicationYear "2016" @default.
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