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- W2584560416 abstract "This paper proposes an efficient power saving scheme in pipelined analog to digital converter (ADC) by scaling residue output four times, called as 4X residue output scaling technique. The proposed technique provides excellent solution for error due to insufficient DC gain, inaccurate settling, limited swing and OTA non linearity. In the 4X residue output scaling, the residue amplifier will bring the interstage output to ±250mV(4X scaled) instead of full scale ±1V. The 4X residue output scaling is implemented in 11 bit, 45MS/s dual channel pipelined analog-to-digital converter. The proposed ADC is realized by four 2.5 bit pipelined stages, followed by 3-bit flash ADC. The proposed dual channel ADC consumes 60mW of power and occupies the 3.5mm2 area in UMC65nm CMOS technology. Post layout simulation with RC-CC (Coupled RC Extraction) achieves the SFDR of 72dB and SINAD of 62 dB at input of 5.5MHz with sampling frequency of 45 MHz." @default.
- W2584560416 created "2017-02-10" @default.
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- W2584560416 date "2016-12-01" @default.
- W2584560416 modified "2023-09-27" @default.
- W2584560416 title "Calibration free power reduction technique for 11Bit, 45MS/s pipelined ADC implementation" @default.
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- W2584560416 doi "https://doi.org/10.1109/indicon.2016.7839134" @default.
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