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- W2587033744 abstract "It is well known that multipliers consume most of the power in DSP computations. Hence, it is very important for modern DSP systems to develop low-power multipliers to reduce the power dissipation. This paper presents 8 ×8 and 16×16 low power row and column bypass multiplier design. The switching activity of the component used in the design depends on the input bit coefficient. This means if the input bit coefficient is zero, corresponding row or column of adders need not be activated. If multiplicand contains more zeros, higher power reduction can be achieved. To reduce the switching activity is to shut down the idle part of the circuit, which is not in operating condition. Further low power adder structure reduces the switching activity. If we can reduce the power consumption of the multiplier block, then we can reduce the power consumption of various digital signal processing chips and communication system." @default.
- W2587033744 created "2017-02-17" @default.
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- W2587033744 date "2013-01-01" @default.
- W2587033744 modified "2023-09-26" @default.
- W2587033744 title "Performance of Improved Multiplier Based On Low-Cost Low-Power Bypassing Technique" @default.
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