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• W2587844224 abstract "This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs." @default.
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• W2587844224 date "2017-06-01" @default.
• W2587844224 modified "2023-10-16" @default.
• W2587844224 title "Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology" @default.
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• W2587844224 doi "https://doi.org/10.1109/tvlsi.2017.2655079" @default.
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