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- W2590604652 abstract "The present title discloses novel concept for high speed computing using essentials of Ancient Indian Vedic Mathematics, modified and implemented using VLSI-FPGA architecture for best performance. The proposed architecture aims to define highly optimized multiplier unit which allows the highly intensive units of Signal Processing, Image Processing, Data Encryption/ Decryption and most other techniques to work at full pelt. To stand at, the title is configured using Hardware Description Language (HDL) around high performance Virtex/ Kintex Series Field Programmable Gate Arrays (FPGA). After implementation the statistical data is analyzed using Synthesis and PAR using Xilinx ISE. The proposed architecture is executed at 1 MHz Frequency and concurrent architecture is developed for 2-bit, 4-bit, 8-bit, 16-bit and 32-bit." @default.
- W2590604652 created "2017-03-03" @default.
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- W2590604652 date "2016-08-01" @default.
- W2590604652 modified "2023-09-26" @default.
- W2590604652 title "VMFPGA: A dynamic approach for high speed computing" @default.
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- W2590604652 doi "https://doi.org/10.1109/iccubea.2016.7860130" @default.
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