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- W2593553191 abstract "Chip based digital isolators are being developed for higher speed and higher isolation capabilities [1, 2]. These make use of various coupling mechanisms such as capacitive coupling [3] and transformer coupling [4]. A limitation of these technologies is that they need to maintain a low separation (distance through insulation DTI<;30μm) through high quality insulators (oxides, polyamides) in order to achieve data rate and isolation performance [2]. These require expensive special process development and special packaging techniques to meet reinforced isolation recommended by IEC 60747-5-5 and VDE 0884-10. Other high-speed die-to-die communication techniques implemented using millimeter-wave and optical solutions are expensive and not designed for isolation. In this work, an isolation technique is proposed where two standard 180nm CMOS dies placed side by side with DTI of more than 500μm, and co-packaged using regular planar MCM flow with package mold compound being the isolation material, achieve asynchronous bidirectional link with >24kV surge isolation capability and greater than 500Mb/s at 175pJ/b. Channel gain is maximized using resonance. Gain is decoupled from channel bandwidth by resetting the channel state variables. This helps in enhancing data rate well beyond what is implied by the bandwidth." @default.
- W2593553191 created "2017-03-16" @default.
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- W2593553191 date "2017-02-01" @default.
- W2593553191 modified "2023-09-27" @default.
- W2593553191 title "25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS" @default.
- W2593553191 cites W2016754692 @default.
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- W2593553191 doi "https://doi.org/10.1109/isscc.2017.7870447" @default.
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