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- W2593733552 abstract "In this paper, a new architecture for accelerating homomorphic function evaluation on FPGA is proposed. The architecture is based on a parallel cached NTT algorithm with an overall time complexity O(√N log √N). The architecture has been implemented on Xilinx Virtex 7 XC7V1140T FPGA that achieves a 60% utilization ratio. The implementation performs 32-bit 216-point NTT algorithm in 23.8μs which is a 2x speedup over the state of the art architectures. The architecture has been evaluated by computing a block of each of the AES and SIMON-64/128 on the LTV and YASHE schemes. The proposed architecture can evaluate the AES circuit using the LTV scheme in 4 minutes while processing 2048 blocks in parallel. This leads to an amortized performance of 117 ms/block, which is the fastest performance reported to the best of our knowledge." @default.
- W2593733552 created "2017-03-16" @default.
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- W2593733552 date "2016-10-01" @default.
- W2593733552 modified "2023-09-25" @default.
- W2593733552 title "Tile-based modular architecture for accelerating homomorphic function evaluation on FPGA" @default.
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- W2593733552 doi "https://doi.org/10.1109/mwscas.2016.7870149" @default.
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