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- W2594879912 abstract "Demonstration of a real-time receiver working with 28 GBd at 32 GSa/s. The signal processing is done on a single FPGA. The resource-saving non-integer oversampling of 8/7 is enabled by a timing synchronization in the frequency domain." @default.
- W2594879912 created "2017-03-16" @default.
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- W2594879912 date "2017-01-01" @default.
- W2594879912 modified "2023-09-23" @default.
- W2594879912 title "168 Gb/s Line Rate Real-Time PAM Receiver Enabled by Timing Recovery with 8/7 Oversampling in a Single FPGA" @default.
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- W2594879912 doi "https://doi.org/10.1364/ofc.2017.w2a.24" @default.
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