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- W2596592286 abstract "Now a days the speed of the multipliers is constrained by the speed of the adders used for partial product expansion. In this Project, we proposed a 4-bit multiplier using a Vedic Multiplier (Urdhva Tiryagbhyam sutra). Vedic is notable for increment information representation. Vedic multiplier estimation is used to enhance the execution sufficiency of the cerebrum boggling tallies. In this project, we proposed a novel 4:2 compressor and two 5:2 compressors outlining. In this arrangement, we decreased lethargy and reach. In the proposed diagram we have reduced the amount of method of reasoning levels, accordingly diminishing the basis delay. In the proposed plot we have reduced the measure of premise levels, thusly diminishing the strategy for thinking deferral. Redirection of the setup is done utilizing Xilinx ISIM and facilitated utilizing Xilinx XST. Proposed compressor diagrams have demonstrated favored execution over existing Vedic algorithm based algorithm." @default.
- W2596592286 created "2017-03-23" @default.
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- W2596592286 date "2016-11-09" @default.
- W2596592286 modified "2023-09-25" @default.
- W2596592286 title "RELIABLE VEDIC MULTIPLIER USING COMPRESSORS" @default.
- W2596592286 hasPublicationYear "2016" @default.
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