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- W2597517312 abstract "SystemVerilog adds hundreds of extensions to the Verilog language. Some of these extensions are intended to represent hardware behavior, and are synthesizable. Other extensions are intended for testbench programming or abstract system level modeling, and are not synthesizable. The IEEE 1800-2005 SystemVerilog standard(1) defines the syntax and simulation semantics of these extensions, but does not define which constructs are synthesizable, or the synthesis rules and semantics. This paper proposes a standard synthesis subset for SystemVerilog. The paper reflects discussions with several EDA companies, in order to accurately define a common synthesis subset that is portable across today's commercial synthesis compilers." @default.
- W2597517312 created "2017-04-07" @default.
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- W2597517312 date "2006-01-01" @default.
- W2597517312 modified "2023-09-23" @default.
- W2597517312 title "A Proposal for a Standard Synthesizable Subset for SystemVerilog-2005: What the IEEE Failed to Define" @default.
- W2597517312 hasPublicationYear "2006" @default.
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