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• W2598433099 abstract "This paper presents a 12b 180 MS/s 0.068 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> 2× time-interleaved pipelined-SAR analog-to-digital converter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a compact area. We improve the noise performance by implementing a mergedresidue-DAC operation in the first-stage ADC. Also, we propose a dual-phase bootstrap technique to improve the sampling linearity in the partial interleaving architecture. The measurement results of the ADC prototype in 65 nm CMOS demonstrate the effectiveness of the proposed calibration through the enhancement of the signal to noise-and-distortion ratio from 51.5 to 60.9 dB at a Nyquist input, leading to a FoM@Nyq of 36.7 fJ/conversion-step." @default.
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• W2598433099 date "2017-07-01" @default.
• W2598433099 modified "2023-10-03" @default.
• W2598433099 title "A 12b 180MS/s 0.068mm² With Full-Calibration-Integrated Pipelined-SAR ADC" @default.
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• W2598433099 doi "https://doi.org/10.1109/tcsi.2017.2679748" @default.
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