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- W2599820220 abstract "This brief presents a wide frequency-range synthesizable multiplying delay-locked-loop with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes output frequency that ranges from 80 kHz to 680 MHz. Owing to the synthesized finely controlled charge pump and phase detector with background offset calibration, the prototype clock generator achieves a 5.2 ps integrated RMS jitter at 680 MHz output while consuming 0.5 mW under a 1.2 V supply." @default.
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- W2599820220 date "2018-03-01" @default.
- W2599820220 modified "2023-09-24" @default.
- W2599820220 title "A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration" @default.
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- W2599820220 doi "https://doi.org/10.1109/tcsii.2017.2689029" @default.
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