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- W2601582588 abstract "This paper proposes a third-order adaptive bandwidth phase-lock loop (PLL) for microprocessor clock generation. The PLLs employed in present-day microprocessors for clock generation require performance parameters such as jitter, lock time, and capture transients to be as low as possible, since the multicore scheme requires fast switching across different pairs of clock frequency and operating voltages. This paper thus proposes to modify the traditional second-order self-biased adaptive bandwidth PLL architecture to a third-order and also a type-III scheme. Simulation carried out in UMC’s 0.18-μm CMOS technology shows significant improvement in jitter performance and settling time with negligible capture overshoot/undershoot. Process corner simulations show that the designed third-order PLL is stable and operates over a wide frequency range from 1 to 2.72 GHz." @default.
- W2601582588 created "2017-04-07" @default.
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- W2601582588 date "2017-01-01" @default.
- W2601582588 modified "2023-09-27" @default.
- W2601582588 title "Design of a Third Order Self Biased Adaptive Bandwidth Phase Lock Loop" @default.
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- W2601582588 doi "https://doi.org/10.1007/978-981-10-2999-8_27" @default.
- W2601582588 hasPublicationYear "2017" @default.
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