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- W2602722699 abstract "The role of multiplier circuitry in real time applications such as microprocessor and digital processing is very prime. The power handling capacity of a multiplier is a key parameter in designing using VLSI technology because the consumption and dissipation of power is a factor which also effects the performance of multiplier. In present paper a technique called bypassing is implemented in conventional shift-and-add multiplier architecture. This technique eliminates unnecessary switching activities responsible for power consumption and also eliminates unnecessary iteration done in the conventional multiplier whenever a zero is encountered in the multiplication process." @default.
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- W2602722699 date "2014-12-01" @default.
- W2602722699 modified "2023-10-16" @default.
- W2602722699 title "Low power Multiplier Design using bypassing and feeder technique" @default.
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