FRINK Linked Data Fragments server

Matches in SemOpenAlex for { <https://semopenalex.org/work/W2605759013> ?p ?o ?g. }

• W2605759013 endingPage "218" @default.
• W2605759013 startingPage "195" @default.
• W2605759013 abstract "New FPGA-based devices with a high degree of reconfigurability that allow dynamic to change architecture and structure are created. These devices improve the efficiency of reconfigurable devices and systems according to the optimal criteria of hardware resources and power consumption, which are decisive for the Green IT Engineering. This class of devices for the implementation of technology the “Reconfigurable computing” is viewed. It is showed that in the dynamic logical structure devices, the configuration dynamically changing depending on the specific solving problem by transmitting information about any given current configuration. As a basic structure for construction of such devices the adaptive logical networks (ALN) are considered. ALN designed for solving of a wide class of problems by means of directly implementing algorithms and by direct mapping of the input data into output data. Unlike already known methods for the synthesis of multilevel logic scheme, two new approaches to the synthesis of such schemes are proposed. The first approach is based on the description of Boolean network by polynomials. In this case coefficients of the polynomial are given by Hadamard matrix. The second approach is based on the description of Boolean network by means Zhegalkin polynomials. An algorithm for partition of the range of Boolean functions is developed. This algorithm (for input data of arbitrary length and a threshold value) allows determining the types of logical functions for each level of ALN. The algorithm is based on the analysis of bit-by-bit of the threshold value for a predetermined threshold relation. The correctness of implementation this algorithm is proved. An example of solving the XOR problem in neural networks by means of a two-layer network is adduced. This network uses proposed by the threshold device and implemented on FPGA chip." @default.
• W2605759013 created "2017-04-28" @default.
• W2605759013 creator A5010378997 @default.
• W2605759013 creator A5056242801 @default.
• W2605759013 creator A5086836483 @default.
• W2605759013 date "2017-01-01" @default.
• W2605759013 modified "2023-09-27" @default.
• W2605759013 title "Resource and Energy Optimization Oriented Development of FPGA-Based Adaptive Logical Networks for Classification Problem" @default.
• W2605759013 cites W121356240 @default.
• W2605759013 cites W1970036573 @default.
• W2605759013 cites W1979438287 @default.
• W2605759013 cites W2003850193 @default.
• W2605759013 cites W2028336034 @default.
• W2605759013 cites W2043558089 @default.
• W2605759013 cites W2076948642 @default.
• W2605759013 cites W2095819354 @default.
• W2605759013 cites W2107101825 @default.
• W2605759013 cites W2131194367 @default.
• W2605759013 cites W2327424706 @default.
• W2605759013 cites W2521068662 @default.
• W2605759013 cites W2521635751 @default.
• W2605759013 cites W2521883755 @default.
• W2605759013 cites W2522373891 @default.
• W2605759013 cites W4254759548 @default.
• W2605759013 cites W42782855 @default.
• W2605759013 doi "https://doi.org/10.1007/978-3-319-55595-9_10" @default.
• W2605759013 hasPublicationYear "2017" @default.
• W2605759013 type Work @default.
• W2605759013 sameAs 2605759013 @default.
• W2605759013 citedByCount "6" @default.
• W2605759013 countsByYear W26057590132017 @default.
• W2605759013 countsByYear W26057590132018 @default.
• W2605759013 countsByYear W26057590132020 @default.
• W2605759013 countsByYear W26057590132022 @default.
• W2605759013 crossrefType "book-chapter" @default.
• W2605759013 hasAuthorship W2605759013A5010378997 @default.
• W2605759013 hasAuthorship W2605759013A5056242801 @default.
• W2605759013 hasAuthorship W2605759013A5086836483 @default.
• W2605759013 hasConcept C11413529 @default.
• W2605759013 hasConcept C141796577 @default.
• W2605759013 hasConcept C149635348 @default.
• W2605759013 hasConcept C187455244 @default.
• W2605759013 hasConcept C196836630 @default.
• W2605759013 hasConcept C2780149590 @default.
• W2605759013 hasConcept C41008148 @default.
• W2605759013 hasConcept C42935608 @default.
• W2605759013 hasConcept C55439883 @default.
• W2605759013 hasConcept C76155785 @default.
• W2605759013 hasConcept C80444323 @default.
• W2605759013 hasConceptScore W2605759013C11413529 @default.
• W2605759013 hasConceptScore W2605759013C141796577 @default.
• W2605759013 hasConceptScore W2605759013C149635348 @default.
• W2605759013 hasConceptScore W2605759013C187455244 @default.
• W2605759013 hasConceptScore W2605759013C196836630 @default.
• W2605759013 hasConceptScore W2605759013C2780149590 @default.
• W2605759013 hasConceptScore W2605759013C41008148 @default.
• W2605759013 hasConceptScore W2605759013C42935608 @default.
• W2605759013 hasConceptScore W2605759013C55439883 @default.
• W2605759013 hasConceptScore W2605759013C76155785 @default.
• W2605759013 hasConceptScore W2605759013C80444323 @default.
• W2605759013 hasLocation W26057590131 @default.
• W2605759013 hasOpenAccess W2605759013 @default.
• W2605759013 hasPrimaryLocation W26057590131 @default.
• W2605759013 hasRelatedWork W194961446 @default.
• W2605759013 hasRelatedWork W1990123009 @default.
• W2605759013 hasRelatedWork W2165747555 @default.
• W2605759013 hasRelatedWork W2289022454 @default.
• W2605759013 hasRelatedWork W2406619057 @default.
• W2605759013 hasRelatedWork W2608372099 @default.
• W2605759013 hasRelatedWork W2811402744 @default.
• W2605759013 hasRelatedWork W2944603686 @default.
• W2605759013 hasRelatedWork W46480492 @default.
• W2605759013 hasRelatedWork W83935621 @default.
• W2605759013 isParatext "false" @default.
• W2605759013 isRetracted "false" @default.
• W2605759013 magId "2605759013" @default.
• W2605759013 workType "book-chapter" @default.