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• W2611700616 abstract "Simulation and verification of the on-die power delivery network (PDN) is one of the key steps in the design of integrated circuits. With the very large sizes of modern grids, verification of PDNs has become very expensive and a host of techniques for grid model approximation have been proposed. These include topological node elimination and full-blown numerical model order reduction (MOR). However, both of these traditional approaches suffer from drawbacks that limit their scalability to very large grids. In this thesis, we propose a novel technique for grid reduction that is a hybrid of both approaches  – the method is numerical but also factors in grid topology. It works by eliminating whole internal layers of the grid at a time, while aiming to preserve the dynamic behavior of the grid. Effectively, instead of traditional node-by-node topological elimination we provide a numerical layer-by-layer block-matrix approach that is both fast and accurate.%%%%M.A.S." @default.
• W2611700616 created "2017-05-12" @default.
• W2611700616 creator A5064752202 @default.
• W2611700616 date "2016-11-01" @default.
• W2611700616 modified "2023-09-27" @default.
• W2611700616 title "A fast metal layer elimination approach for power grid reduction in integrated circuits" @default.
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• W2611700616 hasPublicationYear "2016" @default.
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