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- W2615276056 abstract "This paper presents an analytical framework, supplemented with experimental validation, for optimizing the value of the external gate resistance employed in power conversion circuits using EPC enhancement-mode GaN transistors. A second order analytical model of the GaN device is utilized to determine a function that relates the external gate resistance to the peak gate voltage during turn-on. The results obtained from the analytical model were experimentally validated in a double pulse-test. The derived model allows for optimal selection of gate resistances such that GaN HFETs can be switched as rapidly as possible while keeping them in their safe operating region." @default.
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- W2615276056 date "2017-03-01" @default.
- W2615276056 modified "2023-10-13" @default.
- W2615276056 title "Analytical and experimental optimization of external gate resistance for safe rapid turn on of normally off GaN HFETs" @default.
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- W2615276056 doi "https://doi.org/10.1109/apec.2017.7930966" @default.
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