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• W2621507792 abstract "Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional path delay fault ATPG is not sufficient for hold-time faults. A hold-time fault ATPG is presented to generate robust test patterns. Experiments on large benchmark show that our test patterns are 42% shorter while 38% better in robust fault coverage than 1-detect stuck-at fault test sets. The results justify the need for hold-time fault ATPG." @default.
• W2621507792 created "2017-06-15" @default.
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• W2621507792 date "2017-04-01" @default.
• W2621507792 modified "2023-09-25" @default.
• W2621507792 title "Robust test pattern generation for hold-time faults in nanometer technologies" @default.
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• W2621507792 doi "https://doi.org/10.1109/vlsi-dat.2017.7939647" @default.
• W2621507792 hasPublicationYear "2017" @default.
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