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- W2623904192 abstract "AbstractNowadays, H.264/AVC reaches very high resolutions, flexible depending on the application, which particularly leads to a very large amount of data compression. The motion estimation defines the most-complex process and the most interesting at the same time; its complexity appears with a consumption of more than 60% of total encoding time which make it difficult to achieve real-time encoding required in many video applications, but the interesting part is the flexibility to make its implementation variant according to the application. For this purpose, the following paper presents a speed real-time hardware implementation of integer motion estimation used in H.264/AVC, the method is based on the full-search block-matching algorithm. The proposed architecture calculates best motion vector using a parallel process. It is composed of three processor modules and a comparator three values. Implementation results based on Field Programmable Gate Array devices uses Xilinx Virtex7 XC7VX550T show performance..." @default.
- W2623904192 created "2017-06-15" @default.
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- W2623904192 date "2015-10-02" @default.
- W2623904192 modified "2023-10-08" @default.
- W2623904192 title "Real-time hardware implementation of a speed FSBMA used in H.264/AVC" @default.
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- W2623904192 doi "https://doi.org/10.1080/1206212x.2016.1188554" @default.
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