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- W2629157711 abstract "This paper analyzes the impact of power-supply noise on the performance of high-frequency microprocessors. First, delay models that take this noise into account are proposed for device-dominated and interconnect-dominated timing paths. For typical circuits, it is shown that the peak of the noise is largely irrelevant and that the average supply voltage during switching is more important. It is then argued that global differential noise can potentially have a greater timing impact than common-mode noise. Finally, realistic values for the model parameters are measured on a 2.53-GHz Pentium4 microprocessor using a 130-nm technology. These values imply that the power-supply noise present on the system board reduces clock frequency by 6.7%. The model suggests that the frequency penalty associated with this power-supply noise will steadily increase and reach 7.6% for the 90-nm technology generation." @default.
- W2629157711 created "2017-06-30" @default.
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- W2629157711 date "2004-02-01" @default.
- W2629157711 modified "2023-09-23" @default.
- W2629157711 title "Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors" @default.
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- W2629157711 doi "https://doi.org/10.1109/tadvp.2004.825480" @default.
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