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• W2645022014 abstract "The need for more functionality and higher performance has increased the number of transistors to billions in current processors. A high number of transistors on the same chip area increases the power density, which in turn heats up the devices and lowers the life time of batteries. The increasing demand for devices relying on battery and harvested energies in the Internet of Things (IoT) era has turned the energy efficiency to a main concern and challenge in the silicon industry. Down-scaling the supply voltage is the most effective method for reducing the energy dissipation, and many applications’ minimum energy point is placed at sub- or near-threshold operation region. However, down-scaling the voltage worsens the performance and noise-immunity of the circuits which need to be addressed atdifferent design levels. On-chip memories are among the main building blocks in digital circuits, where their area and energy is often a dominating factor, and consequently, increasing their area and power efficiency is of vital importance. There are numerous on-chip memory categories which serve different design requirements. Standard-cell based memories are known to be highly configurable and voltage scalable, however, they are area inefficient for large memory capacities. On the other hand, the conventional Static Random Access Memory (SRAM) is relatively more area efficient for large capacities, however, it has a limited voltage scaling range which in turn, poses a high energy cost to the system. The main focus of this thesis is on memory power reduction techniques at different abstraction levels from transistor to architectural level. By designing a custom memory-cell, the capacity range in which standard-cell based memories have a higher area efficiency is extended, and a detailed trade off discussion between energy, performance and area is provided. For memories with larger capacities, a low-power SRAM architecture has been designed which is able to operate in the Ultra-Low Voltage (ULV) regime. The performance and reliability is increased by using voltage assist techniques which boost the critical nodes during write and read accesses. Boosted voltages are generated locally by using on-chip charge pumps which are operational in the deep subthreshold regime. Performance, area, and energy efficiency were the main focus in the charge pump realization to maintain the low-power profile of the system. To avoid a continuous charge pump activation, a new charge pumping mechanism has been introduced which generates the required voltage level instantly at a low area cost. This effectively reduces the dynamic energy cost of the system and facilitates the application of a small and low cost charge pump. Toincrease the voltage scalability of the SRAM, a hybrid read architecture has been proposed. This method avoids the voltage limitation of sense-amplifiers and provides a higher performance at ULV with extremely low energy cost. Moreover, to facilitate a reliable communication between design blocks operating at different voltage domains in an SoC, a low-power and area efficient level shifter is introduced and its properties are studied and measured. Finally, it is shown that without paying high area and energy penalties, all design constraints can be met by: a) selecting an architecture with respect to the structure and nature of a design, and, b) realizing the best matching architectures for the required blocks and optimizing them at all design levels. (Less)" @default.
• W2645022014 created "2017-06-30" @default.
• W2645022014 creator A5053540902 @default.
• W2645022014 date "2017-06-16" @default.
• W2645022014 modified "2023-09-23" @default.
• W2645022014 title "Ultra-low Power Design Approaches in Memories and Assist Techniques" @default.
• W2645022014 hasPublicationYear "2017" @default.
• W2645022014 type Work @default.
• W2645022014 sameAs 2645022014 @default.
• W2645022014 citedByCount "1" @default.
• W2645022014 countsByYear W26450220142017 @default.
• W2645022014 crossrefType "dissertation" @default.
• W2645022014 hasAuthorship W2645022014A5053540902 @default.
• W2645022014 hasConcept C119599485 @default.
• W2645022014 hasConcept C127413603 @default.
• W2645022014 hasConcept C149635348 @default.
• W2645022014 hasConcept C165005293 @default.
• W2645022014 hasConcept C165801399 @default.
• W2645022014 hasConcept C172385210 @default.
• W2645022014 hasConcept C24326235 @default.
• W2645022014 hasConcept C2742236 @default.
• W2645022014 hasConcept C41008148 @default.
• W2645022014 hasConcept C48044578 @default.
• W2645022014 hasConcept C68043766 @default.
• W2645022014 hasConcept C77088390 @default.
• W2645022014 hasConceptScore W2645022014C119599485 @default.
• W2645022014 hasConceptScore W2645022014C127413603 @default.
• W2645022014 hasConceptScore W2645022014C149635348 @default.
• W2645022014 hasConceptScore W2645022014C165005293 @default.
• W2645022014 hasConceptScore W2645022014C165801399 @default.
• W2645022014 hasConceptScore W2645022014C172385210 @default.
• W2645022014 hasConceptScore W2645022014C24326235 @default.
• W2645022014 hasConceptScore W2645022014C2742236 @default.
• W2645022014 hasConceptScore W2645022014C41008148 @default.
• W2645022014 hasConceptScore W2645022014C48044578 @default.
• W2645022014 hasConceptScore W2645022014C68043766 @default.
• W2645022014 hasConceptScore W2645022014C77088390 @default.
• W2645022014 hasOpenAccess W2645022014 @default.
• W2645022014 hasRelatedWork W1492552926 @default.
• W2645022014 hasRelatedWork W1502224247 @default.
• W2645022014 hasRelatedWork W168457935 @default.
• W2645022014 hasRelatedWork W1998680654 @default.
• W2645022014 hasRelatedWork W2105318717 @default.
• W2645022014 hasRelatedWork W2126558636 @default.
• W2645022014 hasRelatedWork W2181870072 @default.
• W2645022014 hasRelatedWork W2268694932 @default.
• W2645022014 hasRelatedWork W2275994933 @default.
• W2645022014 hasRelatedWork W2291291075 @default.
• W2645022014 hasRelatedWork W2320798209 @default.
• W2645022014 hasRelatedWork W2333727899 @default.
• W2645022014 hasRelatedWork W2423875452 @default.
• W2645022014 hasRelatedWork W2574367695 @default.
• W2645022014 hasRelatedWork W2783150416 @default.
• W2645022014 hasRelatedWork W2896616306 @default.
• W2645022014 hasRelatedWork W2922307058 @default.
• W2645022014 hasRelatedWork W2980976157 @default.
• W2645022014 hasRelatedWork W3035110523 @default.
• W2645022014 hasRelatedWork W3127432421 @default.
• W2645022014 isParatext "false" @default.
• W2645022014 isRetracted "false" @default.
• W2645022014 magId "2645022014" @default.
• W2645022014 workType "dissertation" @default.