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- W26696136 abstract "This paper discusses how designing the high-frequency distribution system to allow HP's new 32-bit VLSI processor to operate at 18 mhz proved to be a significant design challenge. The chips required 6 v, two-phase, nonoverlapping clocks with rise times less than 6 ns and overshoot/undershoot less than 1 v. It was decided early in the project that, because of area constraints, the processor chips would not buffer their clocks. However the RAM chips do provide some buffering. Hence the capacitive loading components vary from approximately 300 pf per phase for a CPU chip to approximately 30 pf per phase for a ram chip. In addition, the capacitive loading presented is highly variable because of the dynamic circuits used and depends on which circuits are active. Worst-case tolerances produce capacitive specifications that can vary +or- 30percent and cause unbalanced loads on each phase." @default.
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- W26696136 date "1983-08-01" @default.
- W26696136 modified "2023-09-23" @default.
- W26696136 title "18-mhz clock distribution system" @default.
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