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- W2685029256 abstract "In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits." @default.
- W2685029256 created "2017-06-30" @default.
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- W2685029256 date "2017-02-01" @default.
- W2685029256 modified "2023-09-29" @default.
- W2685029256 title "Asymmetrical length biasing for energy efficient digital circuits" @default.
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- W2685029256 doi "https://doi.org/10.1109/lascas.2017.7948060" @default.
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