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• W2695843206 abstract "The Moore’s Law has benefited us a lot since 1970s. As conceptualized by R. Dennard [1],one can obtain transistors with higher speed and lower energy consumption in reducingthe critical dimensions and keeping the electrical field constant. This concept made thecontinuous trend of increase in integration density of CMOS (Complementary MetalOxide-Silicon) technology possible. Since 1970s, the number of components per chip has doubledevery two years [2]. As mentioned in the ITRS (International Technology Roadmap forSemiconductors) 2007 [3], the operation frequency of a transistor will reach 12 GHz andthe number of transistors contained in a single chip may be 12 billion in 2020.With the dimension shrinking to nanometer, or Deep Submicron Meter (DSM), manychallenges have risen, one of which is the dramatically increasing probability of soft errorsinduced by Single Event Upsets (SEUs) or Single Event Transients (SETs). Normally, thesekinds of soft errors often happened in the memory cells and rarely occurred in the logiccircuits on the ground level. However, the increased operation frequency, the lower supplyvoltage and the reduced noise margin have made the transient current pulses induced byalpha particles or high-energy neutrons much easier to be captured by the filp-flops atthe outputs of logic circuits. Consequently, the reliability of logic circuits (including theevaluation methodologies) in nanometer regime have been an important design criterionin ICs design [4].Another challenge accompany with the CMOS dimension scaling to nanometer is thatthe thermal noise is not neglectable any more. As pointed in [2], the RMS of thermalnoise will increase during miniaturization. The probability of the thermal noise crossingthe voltage threshold also steadily increases with the reduction of the noise margin [2].Thus the noise-immunity of logic circuits is also an important concern in ICs designs.Therefore, with CMOS technology scaling into DSM or nanometers, the behaviour oflogic gates, the output of logic functions or even the services of systems are not determin-istic but probabilistic. The reliability of probabilistic circuits, induced by the soft errorsand noise, draws much more attention in modern IC designs.This thesis concentrates on the reliability evaluation methodology improvements andthe general cost-effective noise-tolerant circuit designs.An efficient evaluation methodology based on Probability Transfer Matrix (PTM) isproposed to obtain the accurate reliability of a combinational circuit. Compared withthe traditional PTM, the proposed PTM (denoted as ECPTM) can dramatically reducethe penalty in time consumption and memory usage. A general analytic tool has beendeveloped to get the reliability of a circuit with its netlist file. The efficiency improvementof the proposed method is verified with practical bench circuits.This thesis also presents a general cost-effective noise-immune design structure of logicfunctions. This design structure is based on Markov Random Fields (MRF) and is suitablefor all the basic logic gates as well as complex logic functions involving several logic gates.This structure has been verified through simulations done in SPICE using the BerkeleyPredictive Technology Model (BPTM) 65nm CMOS Technology [5] and in Spectre basedon ST 65nm CMOS models.Furthermore, this thesis proposes a model to analyze the reliability issues induced byboth SETs and noise. Mathematical conditions are derived in order to improve the SETsrobustness and noise-immunity at the same time." @default.
• W2695843206 created "2017-06-30" @default.
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• W2695843206 date "2014-10-15" @default.
• W2695843206 modified "2023-09-24" @default.
• W2695843206 title "Reliability of probabilistic circuits" @default.
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