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- W2734816345 abstract "To enhance System on a Chip (SoC) yield this paper proposes understanding IP contributions. Data structures specific to IP design characteristics for test manufacturing data system can support this goal. This data provides a knowledge foundation and connects the knowledge traditionally siloed into Design, Fab and Test areas. Such a knowledge enhances the ability to comprehend manufacturability at the IP level. Metrics specific to IP blocks are proposed. This paper concludes with potential benefits for manufacturing engineers." @default.
- W2734816345 created "2017-07-21" @default.
- W2734816345 creator A5000151127 @default.
- W2734816345 date "2017-05-01" @default.
- W2734816345 modified "2023-09-26" @default.
- W2734816345 title "Enhancing yield learning on SoC designs by tracking IP manufacturability" @default.
- W2734816345 doi "https://doi.org/10.23919/mipro.2017.7966557" @default.
- W2734816345 hasPublicationYear "2017" @default.
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